Internal OCXO
Ext. 10 / 100 MHz
Facility clock
What it takes to hold timing jitter under five picoseconds.
Jitter isn't a figure you add at the end of a design. It's the sum of every stage between the reference input and the output connector — and every one of those stages is ours.
Inside the instrument
Four stages between your reference and your output edge.
A single module and a hundred-channel chassis share one architecture. Each stage adds a known contribution to the total — and each one has a design lever attached to it.
01
Input & lock
Selection, buffering, lock detection
02
PPL
Phase lock, multiplication, loop-bandwidth cleanup
03
Delay core
Coarse counter on the clock edge, then fine analog interpolation
1 PS STEPS
04
Output stage
Width, polarity, level — 10 V into 50 Ω
05
Control layer
Ethernet RJ45 / SFP · PXI, PXIe, cPCI · USB, RS232, GPIB, VXI, VME — driven from EPICS, Tango, Python or LabVIEW
Up to 100 independent channels
Same command set across families
Drivers written in-house
Timing jitter
Four places jitter comes from.
Timing jitter is the shot-to-shot deviation of a real edge from where the clock says it should be. It's random, so it's quoted as an RMS value over a stated population — never as a single worst case.
Reference phase noise
- Everything downstream inherits the short-term stability of the source. A noisy input sets a floor no design can lift.
PLL loop noise
The loop that cleans the reference filters noise in one band and passes it in another. Bandwidth is the trade-off.Interpolator quantisation
The fine stage places the edge between two clock periods. Its step sets resolution; its linearity sets how honest that is.Slew rate & threshold
Amplitude noise becomes timing noise at the receiver. A slow edge into a noisy threshold turns millivolts into picoseconds.
Same instability, two views
Jitter is the time-domain answer: how far an edge lands from its ideal position, in seconds. Phase noise is the frequency-domain answer: noise power at a given offset from the carrier, in dBc/Hz.
Which one you need
Ask for RMS jitter when you trigger discrete events. Ask for phase noise when you distribute a continuous clock. Integrating phase noise over a defined band converts it to jitter — so always state the band.
Disciplines
Four disciplines, one building.
A timing spec is decided where analog electronics, optics, metrology and embedded software meet. In four different companies, it gets negotiated. In one room near Toulouse, it gets designed.
Optical instrumentation
Optical links keep the edge sharp across a building and isolate the two ends electrically. Same competence covers streak and CCD camera interfacing.
Embedded software
Firmware and drivers written in-house, one command set across families. An instrument arrives as a device on your control system, not a box to wrap.
Analog & digital electronics
Matched propagation paths, isolated supplies, comparators chosen for their edge behaviour. FPGA logic sequences and counts — it never handles the fine timing.
Metrology
We build our own test benches, because commercial instruments rarely resolve what we need to prove. Nothing is specified before it is measured.
Clock & trigger distribution
Getting the same picosecond to the other end of the building.
Generating a precise edge is one problem. Delivering it unchanged to forty instruments across a site is another. Time transfer answers what time is it here; trigger distribution answers fire now, within a few picoseconds. Most installations need both layers — we build the second.
Tell us what the instrument has to do. We'll tell you how.
Calibration, repair, upgrade or a custom development: describe it in a few lines and an engineer answers within two working days — with a real technical response, not an acknowledgement of receipt.
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